1. Field of the Invention
This invention relates to a clock signal reproduction device for reproducing a clock signal from an input digital signal.
2. Description of the Related Art
In a communication system such as a communication system, which uses digital signals, it is general to provide a clock signal reproduction device in order for a clock signal used for signal processing to be reproduced from an input signal received from another party, so that changes in the clock frequency of the input signal can always be followed.
FIG. 33 shows an example of a conventional clock signal reproduction device, and FIG. 34 shows the frequency characteristics of the clock signal reproduction device in this conventional example in an open loop condition. This clock signal reproduction device is disclosed in Japanese Unexamined Patent Application, First Publication, No. 63-249976 as a clock signal reproduction device.
The clock signal reproduction device of the above conventional example, shown in FIG. 33, comprises; a gate 101, a phase comparator 102, an adder 103, a loop filter 104, a VCO (Voltage Controlled Oscillator) 105, a frequency divider 106, and a frequency comparator 107.
Using a drop out signal, the gate 101 blocks an input digital data signal. The phase comparator 102 produces an output corresponding to the phase difference between the digital signal from the gate 101 and the clock signal from the frequency divider 106.
The frequency comparator 107 generates an output corresponding to the frequency difference between the reference signal and the clock signal. The adder 103 adds the output from the phase comparator 102 and the output from the frequency comparator 107. The loop filter 104, as shown in FIG. 34(a), has flat frequency characteristics between frequency f111 and frequency f112, and generates a voltage corresponding to the addition result from the adder 103 to be output to the VCO 105.
The whole clock signal reproduction device has the frequency characteristics as shown in FIG. 34(b) in an open loop condition, and generates a signal of a frequency corresponding to the output voltage from the loop filter 104. The frequency divider 106 divides the signal generated by VCO 105 to produce a clock signal.
Next is a description of the operation of the clock signal reproduction device shown in FIG. 33. In the phase comparator 102, an output corresponding to the phase difference between the input digital signal and the clock signal is generated, and also in the frequency comparator 107 an output corresponding to the frequency difference between the clock signal and the reference signal is generated. Then in the adder 103, the output of the phase comparator 102 and the output of the frequency comparator are added. The bandwidth of the voltage signal of he addition result is limited by the loop filter 104, the obtained voltage being applied to the VCO 105, and thus the signal generated by the VCO 105 is divided by the frequency divider 106 to produce a clock signal. Therefore, according to the clock signal reproduction device shown in FIG. 33, depending on the dominant output of either the phase comparison result between the input digital signal and the clock signal, or the frequency comparison result between the clock signal and the reference signal, the operation is performed in either phase comparison mode or frequency comparison mode, and hence it is possible to generate a clock signal that is synchronized to the input digital signal or the reference signal.
However, with the clock signal reproduction device of the conventional example shown in FIG. 33, since the adder 103 comprises an analog circuit, if the linearity of the adder 103 is poor then it affects the addition result. Therefore, it is not possible to obtain an addition result that reliably corresponds to the output based on the phase difference from the phase comparator 102 and the output based on the frequency difference from the frequency comparator 107, and hence a clock signal of a frequency corresponding to the input digital signal cannot be reproduced.
Furthermore, since the adder 103 comprises an analog circuit, there is a possibility that dispersion in the operation and the like occurs due to manufacturing faults. Therefore, a consistent clock signal reproduction device cannot be realized.
Moreover, with the clock signal reproduction device of this conventional example, during the operation in phase comparison mode the output of the frequency comparison result may cause external interference and prevent normal operation.
In this respect, a clock signal reproduction device is proposed wherein such problems are solved by separating the phase comparison mode system and the frequency comparison mode system completely.
FIG. 35 shows another example of a conventional clock signal reproduction device, which is disclosed as an asynchronous data demodulation circuit in Japanese Unexamined Patent Application, First Publication No. 11-41222.
In the clock signal reproduction device of this conventional example, as shown in FIG. 35, the construction comprises; a phase comparison section 201, a phase/frequency comparison section 202, a selection section 203, a loop filter 204, a VCO 205, a frequency detecting section 206, and a timer 207.
The clock signal reproduction device in FIG. 35 does not have an analog adder circuit, so that such problems as lack of consistency due to manufacturing faults as in the conventional example in FIG. 33 have been solved.
By comparing the phases of the input data signal and the output clock signal, the phase comparison section 201 generates an UP signal for increasing the frequency of the output clock signal, or a DN signal for reducing it. By comparing the frequencies of the output clock signal and the reference clock signal, the phase/frequency comparison section 202 generates an UP signal for increasing the frequency of the output clock signal, or a DN signal for reducing it. The selection section 203 selects the output of the phase comparison section 201 or the phase/frequency comparison section 202 and outputs the UP signal or the DN signal as the selection result. The loop filter 204 contains a charge pump circuit, which supplies a signal obtained by direct current reproduction or bandwith limiting of the input signal to the VCO 205. The VCO 205 signal oscillates at a frequency corresponding to the output voltage of the loop filter 204. The frequency detecting section 206 calculates the frequencies of the output clock signal and the reference clock signal each time a system reset signal is input, and when the difference between the calculated results exceeds a predetermined value, it generates an output signal Eo. The timer 207 is driven by the presence of the signal Eo, and outputs a signal that is significant during a certain operation period. The selection section 203 selects the output of the phase/frequency comparator 202 during the period that the output of the timer 207 is present, and selects the output of the phase comparison section 201 during the other period.
Next is a description of the operation of the clock signal reproduction device shown in FIG. 35. In the condition where synchronization of the output signal of the VCO 205 to the frequency of the input data signal is established, the frequency detecting section 206 does not generate an output. Accordingly, the timer 107 is in an inactive condition, and the selection section 203 selects the output of the phase comparison section 201. In this condition, the clock signal reproduction device performs a PLL (Phase Locked Loop) operation in phase comparison mode between the input data signal and the output clock signal to control such that the output clock signal frequency follows the input data signal.
On the other hand, in the condition where the output clock signal of the VCO 205 is out of synchronization to the input data signal frequency, the timer 207 operates by the presence of the output signal Eo from the frequency detecting section 206, and the selection section 203 selects the output of the phase/frequency comparison section 202 during the timer operating period. In this condition, the clock signal reproduction device operates as a PLL in phase/frequency comparison mode between the reference clock signal and the output clock signal to control the synchronization of the output clock signal frequency to the reference clock signal. In this case, by selecting a time To that is necessary and sufficient to establish synchronization for the operating period, since the clock signal reproduction device is in synchronization with the reference clock signal when the operating time To is over, it is possible to operate in synchronization with the input data signal immediately after the selection section 203 reselects the output of the phase comparison section 201.
However, with respect to the clock signal reproduction device of the conventional example shown in FIG. 35, there is a problem in that jitter tolerance, being the range in which the clock signal generation operation can continue to follow variations in the frequency of the input data signal, is low.
This is because of the case where if the phase of the input data signal changes gradually after the phases of the input data signal and the output data signal are synchronized, it is preferable not to judge it to be out of synchronization, but to follow it continuously. However, since the size of the predetermined phase difference when switching from phase comparison mode to phase frequency comparison mode and the size of the predetermined phase difference when switching back are the same, the two predetermined phase differences must be set to the same value to compensate for a predetermined phase difference when operating such that the phase difference is as small as possible.
Furthermore, in this conventional example, there is a problem in that before returning to phase comparison mode at the time of an out of synchronization condition, there is a possibility of wasted time.
This is because of the case where since the time to return to phase comparison mode is set to a predetermined time that is fixed by the timer 207, even when synchronization is established early, it must wait until the timer period is completed, and hence there is wasted time.